1. Field of the Invention
The present invention relates in general to verifying designs and in particular to verifying a logic function in a netlist. Still more particularly, the present invention relates to a system, method and computer program product for performing minimization of input count during structural netlist overapproximation.
2. Description of the Related Art
With the increasing penetration of microprocessor-based systems into every facet of human activity, demands have increased on the microprocessor development and production community to produce systems that are free from data corruption. Microprocessors have become involved in the performance of a vast array of critical functions, and the involvement of microprocessors in the important tasks of daily life has heightened the expectation of reliability of calculative results. Whether the impact of errors would be measured in human lives or in mere dollars and cents, consumers of microprocessors have lost tolerance for error-prone results. Consumers will not tolerate, by way of example, miscalculations on the floor of the stock exchange, in the medical devices that support human life, or in the computers that control their automobiles. All of these activities represent areas where the need for reliable microprocessor results has risen to a mission-critical concern.
Formal verification techniques, semiformal verification techniques and simulation provide powerful tools for discovering errors and verifying the correctness of logic designs. Formal verification techniques, semiformal verification techniques and simulation frequently expose probabilistically uncommon scenarios that may result in a functional design failure. Additionally, formal verification techniques provide the opportunity to prove that a design is correct (e.g., that no failing scenario exists).
One commonly-used approach to formal, semiformal, and simulation analysis for applications operating on representations of circuit structures is to represent the underlying logical problem structurally (as a circuit graph), and to perform explicit or symbolic evaluation of that circuit graph.
In such an approach, a logical problem is represented structurally. Explicit simulation-based approaches to hardware verification are scalable to very large designs, though suffer from the coverage problem that generally limits them to yielding exponentially decreasing coverage with respect to design size. Formal verification techniques overcome the coverage problem of simulation, yielding exhaustive coverage, though suffer from computational complexity that limits their application to smaller designs.
Formal verification techniques generally require exponential resources with respect to the number of state elements and inputs of a design under verification. Various techniques have been proposed to address the reduction in the number of state elements. For example, the technique of overapproximating the behavior of a design by replacing certain internal gates by inputs (referred to as “localization”) has been proposed, which effectively causes any logic which fans out to the signals being referred to by a property solely through the injected cut-points to be removed from the domain of the verification problem. An unfortunate characteristic of localization is that the cut-point insertions tend to substantially increase the number of inputs in the design, which can be detrimental to subsequent proof analysis techniques sensitive to that metric, such as binary decision diagram-based reachability analysis.
Under the prior art, no adequate solution exists for performing minimization of input count during structural netlist overapproximation.